This invention relates to a physical address developing unit for a data processing (DP) system.
A method for forming a physical address in main memory field is proposed in "Processor Handbook PDP 11/45", pp. 147-165, published in 1971 by Digital Equipment Corporation. With this method, the designation of each of the physical addresses in the memory field divided into a plurality of segments is achieved by the use of a corresponding base address. More particularly, a plurality of base addresses corresponding to the segments are stored in a segment base address register (SBAR) bank. A physical address is produced by the sum of a selected base address corresponding to a segment and a displacement from the segment. Stated in detail, a virtual address of 16 bits (consisting of a 3-bit segment and a 13-bit displacement) is assumed to develop a physical address of 18 bits by adding an 18-bit base address in an SBAR selected by the segment of the virtual address to the displacement given by the same virtual address.
However, this method has the following disadvantages:
(a) Since the segment size is determined by the 13-bit SBAR, the assumable size is limited within the address space of 8 kilobytes.
(b) The memory field accessible at one time without changing the content of the SBAR is restricted within the space of 64 kilobytes.
(c) To achieve such an addressing operation, a desired segment field must be particularly prepared within each virtual address. Besides, much attention must be paid so that the displacement defined in each virtual address does not disturb the contents of the segment fields preset in SBAR bank, since each virtual address is produced by the sum of the SBAR content and the displacement as discussed above.
To solve the above-mentioned disadvantages, another addressing method is proposed in "AmZ 8000 Family Reference Manual, Principles of Operation, AmZ 8001/2 Processor Instruction Set," pp. 16-19, published in 1979 by Advanced Micro Devices, Inc. This second method permits the achievement of a data processing (DP) system with a comparatively small number of address bits, which may use the maximum possible memory field.
Since the second method employs a translation table corresponding to the SBAR bank used in the first addressing method, all the disadvantages (a) to (c) of the first method can be eliminated. However, with the second method, at most 8 base registers are used of the 16 registers, in addition to a pair of base registers, that are prepared. Consequently, an efficient addressing operation is not achieved.